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PROJECT TITLE :

High-Performance NB-LDPC Decoder With Reduction of Message Exchange - 2016

ABSTRACT:

This paper presents a completely unique algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, that decreases the storage resources and also the wiring congestion and, so, will increase the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm contains a negligible performance loss for high-rate codes with GF(16) and GF(32) and a performance loss smaller than zero.07 dB for top-rate codes over GF(64). Additionally, a layered decoder architecture is presented and implemented on a ninety-nm CMOS method for the subsequent high-rate NB-LDPC codes: (2304, 2048) over GF(sixteen), (837, 726) over GF(thirty two), and (1536, 134four) over GF(64). In all cases, the achieved throughput is over 1 Gb/s.


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CMOS Integrated Circuits Error Statistics Parity Check Codes Minimax Techniques Wiring Check Node (CN) Processing High Rate High Speed Layered Schedule Non-Binary Low-Density Parity-Check (NB-LDPC) VLSI Design
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