Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding - 2016 PROJECT TITLE : Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding - 2016 ABSTRACT: The sphere of approximate computing has received important attention from the research community in the past few years, particularly within the context of numerous Signal Processing applications. Image and video compression algorithms, like JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision because of human imperceptibility, that will be exploited to comprehend highly power-economical implementations of these algorithms. But, existing approximate architectures usually fix the level of hardware approximation statically and don't seem to be adaptive to input knowledge. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption with the goal of maintaining a explicit Peak Signal-to-Noise Ratio (PSNR) threshold for any video. Toward this finish, we have a tendency to style reconfigurable adder/subtractor blocks (RABs), that have the ability to modulate their degree of approximation, and subsequently integrate these blocks within the motion estimation and discrete cosine remodel modules of the MPEG encoder. We have a tendency to propose two heuristics for automatically tuning the approximation degree of the RABs in these 2 modules throughout runtime primarily based on the characteristics of every individual video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of onep.c-10%) across completely different videos while achieving a power saving up to 38percent over a conventional nonapproximated MPEG encoder design. Note that though the proposed reconfigurable approximate design is presented for the precise case of an MPEG encoder, it can be simply extended to different DSP applications. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Adders Arithmetic Codes Discrete Cosine Transforms Motion Estimation Video Coding Approximate Circuits Approximate Computing Low Power Design Quality Configurable High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier - 2016 Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes - 2016