Low-power, parasitic-insensitive interface circuit for capacitive microsensors

PROJECT TITLE :

Low-power, parasitic-insensitive interface circuit for capacitive microsensors

ABSTRACT:

Capacitive transduction is ubiquitously employed at macro- and particularly micro-scales because of their simple structure and stability. This study proposes a topology for an occasional-power readout circuit for differential capacitive sensors. The circuit includes 2 switched-capacitor blocks that turn out signals that are proportional to the difference and add of the sense capacitors. Outputs of those two blocks are fed to an analogue divider to provide a pulse whose width is proportional to the ratio of the distinction to sum of the sense capacitors. Additionally to providing adjustable sensitivity and noise levels, this additionally reduces the sensitivity of the sensor to common-mode parasitics at the circuit input. The circuit topology was realised in an exceedingly commonplace CMOS 0.35 μm technology with a total chip area of 330 μm × 600 μm. The performance of the fabricated circuit was evaluated by pairing it with a micromechanical variable capacitor. Experimental results demonstrated the capability of the circuit to resolve a hundred and sixty aF of differential capacitance with a complete power consumption of 720 μW whereas remaining insensitive to common-mode parasitic capacitances.

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