A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture


A 3 MHz-to-1.eight GHz, 94 μW-to-nine.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology is presented. During this paper, a cyclic [*fr1]-delay-line architecture that uses the same sort of delay lines for cyclic delay determination and coarse locking is proposed and used to realize the look goals of little footprint and fast locking for a large operating frequency range. Also, a new delay structure is developed for the cyclic delay units and coarse delay line. Along with clock gating, that is used to cut back power consumption in the lock-in state irrespective of the clock frequency, the automated bypassing of the cyclic operation is developed and used to scale back power consumption during high-frequency operation. Through the employment of proposed techniques, the active area is reduced to solely 0.0153 mm 2, and therefore the operating frequency vary is from three MHz to 1.eight GHz. The measurement results show that the proposed ADDLL achieves a peak-to-peak jitter of 3 ps with 9.five mW power consumption when operated at one.eight GHz.

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