Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015
A brand new style theme meant to boost the performance of true single-part clocked (TSPC) twin modulus prescalers is presented. 2 branches of TSPC D flip-flops are merged to reduce each power and device count. An HSPICE simulation of the proposed scheme demonstrates the highest power potency and best power-delay product among the referenced designs.
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