32-bit RISC CPU Based on MIPS

ABSTRACT:

In this paper, we analyze MIPS instruction format-, instruction data path-, decoder module function and design theory basend on RISC CPUT instruction set. Furthermore, we design instruction fetch (ZF) module of 32-bit CPUbased on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module -, address arithmetic module-, check validity of instruction module-, synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on Quartus ll.

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