A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM - 2016
Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale features a promising future; QCA is an fascinating technology for building memory. The proposed design and simulation of a replacement memory cell structure primarily based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This project presents the planning and simulation of a 16-bit x 32-bit SRAM with a replacement structure in QCA. Since QCA is a pipeline, this SRAM contains a high operating speed. The sixteen-bit x 32-bit SRAM encompasses a new structure with a thirty two-bit width designed and implemented in QCA. It has the flexibility of a standard logic SRAM which will offer scan/write operations frequently with minimum delay. The 16-bit x thirty two-bit SRAM is generalized and an n x 16-bit x 32-bit SRAM is implemented in QCA. Novel sixteen-bit decoders and multiplexers (MUXs) in QCA are presented that are designed with a minimum range of majority gates and cells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA employing a signal distribution network to avoid the coplanar drawback of crossing wires. The QCA-based mostly SRAM cell was compared with the SRAM cell primarily based on CMOS. Results show that the proposed SRAM is a lot of economical in terms of space, complexity, clock frequency, latency, throughput, and power consumption.
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