DCT/IDCT finds potent application in the field of image and signal processing. In this paper, we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low power implementations as in, but in this novel implementation we prove that a lower power implementation can be done which also increases speed(of what?) by approximately five times over that of conventional implementations. The implementation of both non-pipelined (conventional) and pipelined method uses Xilinx XC3S4000 FPGA. The DCT/IDCT is found using the most common and optimum method of taking inputs as set of eight data elements. Finally, a comparison of thespeeds of both implementations is made, and the speed up achieved by the low power pipelined implementationof 1D-DCT/IDCT is presented.
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