|
126 |
A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC - 2017 |
Abstract
|
|
127 |
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters - 2017 |
Abstract
|
|
128 |
Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic - 2017 |
Abstract
|
|
129 |
Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM - 2017 |
Abstract
|
|
130 |
Design and Applications of Approximate Circuits by Gate-Level Pruning - 2017 |
Abstract
|
|
131 |
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities - 2017 |
Abstract
|
|
132 |
Efficient RNS Scalers for the Extended Three-Moduli Set(2n -1; 2n+p; 2n + 1) - 2017 |
Abstract
|
|
133 |
Area-time Efficient Architecture of FFT-based Montgomery Multiplication - 2017 |
Abstract
|
|
134 |
Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition - 2017 |
Abstract
|
|
135 |
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA - 2017 |
Abstract
|
|
136 |
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA - 2017 |
Abstract
|
|
137 |
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division - 2017 |
Abstract
|
|
138 |
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials - 2017 |
Abstract
|
|
139 |
A Structured Visual approach to GALS Modelling and Verification of Communication Circuits - 2017 |
Abstract
|
|
140 |
Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm - 2017 |
Abstract
|
|
141 |
Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression - 2017 |
Abstract
|
|
142 |
Powering Wearable Sensors with a Low-Power CMOS Piezoelectric Energy Harvesting Circuit - 2017 |
Abstract
|
|
143 |
Low Power 8-bit ALU Design Using Full Adder and Multiplexer - 2017 |
Abstract
|
|
144 |
Evolutionary Approach to Approximate Digital Circuits Design - 2017 |
Abstract
|
|
145 |
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology - 2017 |
Abstract
|
|
146 |
Design And Analysis Of Combinational Coding Circuits Using Adiabatic Logic - 2017 |
Abstract
|
|
147 |
Analysis and Design of the Classical CMOS Schmitt Trigger in Sub threshold Operation - 2017 |
Abstract
|
|
148 |
A Single-ended with Dynamic Feedback Control 8T Sub threshold SRAM Cell - 2017 |
Abstract
|
|
149 |
A Low Power, Low Noise Amplifier For Recording Neural Signals amplification in SCL 180nm - 2017 |
Abstract
|
|
150 |
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply - 2017 |
Abstract
|
