PROJECT TITLE :

A Structured Visual approach to GALS Modelling and Verification of Communication Circuits - 2017

ABSTRACT:

During this paper, a completely unique globally asynchronous regionally synchronous (GALS) modeling and verification tool is introduced for xMAS circuits. The tool provides a structured atmosphere for GALS in which organization of the modeling and verification enables it to handle a selection of implementation tasks facilitating a method that would preferably be troublesome for the top user. The tool provides verification techniques at totally different levels. A replacement unfolding algorithm is presented that uses structured prevalence nets. A completely unique illustration for deadlocks is introduced using deadlock relations enabling the causality of local and international deadlocks to be visualized. This helps in the investigation of total or partial system shutdown. In specific, the approach allows the visualization of point-to-point causality of problems occurring between totally different parts of the system which are more tough to analyze. Still totally different varieties of deadlock related to the synchronizer can be detected. The work presented here provides structured visualization capability facilitating the analysis of complex communication systems.