Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing - 2015 PROJECT TITLE: Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing - 2015 ABSTRACT: Speed and the performance of any digital signal processor are largely determined by the efficiency of the multiplier units gift at intervals. The use of Vedic mathematics has resulted in vital improvement in the performance of multiplier architectures used for top speed computing. This project proposes four-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Method technology using Cadence EDA tool. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2015 Low power compressor based MAC architecture for DSP applications - 2015