A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2015 PROJECT TITLE: A High-Speed FPGA Implementation of an RSD-Based ECC Processor - 2015 ABSTRACT: In this project, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs in depth pipelining techniques for Karatsuba-Ofman technique to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, that results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction theme. The proposed processor performs single-purpose multiplication using points in affine coordinates in two.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Analysis of ternary multiplier using booth encoding technique - 2015 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications - 2015