FPGA implementation of vedic floating point multiplier - 2015 PROJECT TITLE: FPGA implementation of vedic floating point multiplier - 2015 ABSTRACT: Most of the scientific operation involve floating purpose computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a important role in any digital style. Even though numerous multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic arithmetic involves application of sixteen sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered during this work. An IEEE-754 based Vedic multiplier has been developed to carry out each single precision and double precision format floating purpose operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been created use of while implementing these algorithms and a resource utilization and timing performance based comparison has additionally been made. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier - 2015 FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers - 2015
