A Case for Hybrid Discrete-Continuous Architectures


Current technology trends indicate that power- and energyefficiency can limit chip throughput in the longer term. Current solutions to these issues, either within the manner of programmable or fixed-function digital accelerators can soon reach their limits as microarchitectural overheads are successively trimmed. A important departure from current computing strategies is required to carry forward computing advances beyond digital accelerators. In this paper we have a tendency to describe how the energy-efficiency of a big class of issues can be improved by employing a hybrid of the discrete and continuous models of computation instead of the ever-present, ancient discrete model of computation. We have a tendency to present preliminary analysis of domains and benchmarks which will be accelerated with the new model. Analysis shows that machine learning, physics and up to 1-third of SPEC, RMS and Berkeley suite of applications will be accelerated with the new hybrid model.

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