PROJECT TITLE :

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

ABSTRACT:

This transient presents a 2-port disturb-free 9T subthreshold static random access memory (SRAM) cell with freelance single-ended read bitline and write bitline (WBL) and cross-point information-aware write structure to facilitate robust subthreshold operation and bit-interleaving design for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist theme where the timing of areaefficient boosted write wordline and negative WBL are aligned and triggered/initiated by the identical low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. forty-nm low-power (40LP) CMOS. Full functionality is achieved for VDD ranging from 1.five to zero.32 V without redundancy. The measured most operation frequency is 260 MHz (450 kHz) at one.1 V (0.32 V) and 25 °C. At zero.325 V and 25 °C, the chip operates at 600 kHz with 5.78 μW total power and 4.69 μW leakage power, giving a pair of× frequency improvement compared with three hundred kHz of our previous seventy two-kb 9T subthreshold SRAM style in the identical 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and twenty five °C is zero.267 pJ/bit, a twenty three.7% improvement over the 0.350 pJ/little bit of our previous style.