PROJECT TITLE :

Noise Modeling and Analysis of SAR ADCs

ABSTRACT:

A generic statistical model for calculating input-referred noise of an analog-to-digital converter (ADC) impaired by thermal noise is proposed. Based on this model, detailed statistical analyses are performed on 3 successive approximation register (SAR) ADCs and the analytical results obtained are verified with Monte Carlo simulations. To compare the input-referred noise of various SAR ADC architectures, a noise gain issue is proposed, that relates the noise at the comparator input (high plate of capacitor array) to that at the ADC input. The noise gain factors are computed and compared for all three ADCs analyzed. The model and methodology presented during this paper can be applied to numerous ADC architectures for circuit style and optimization.