PROJECT TITLE :

Low Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

ABSTRACT:

The designs of resistive RAM (ReRAM) macros are limited by one) a little sensing margin, restricted read- VDDmin, and slow scan access time (TAC) caused by a high cell-resistance and tiny cell-resistance-ratio (R-ratio) and a couple of) poor power integrity and increased energy waste thanks to a large SET dc-current (IDC-SET) ensuing from the wide distribution of write (SET)-times (TSET). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately one.eight+x bigger sensing margin for lower VDD min and a 1.7+x faster browse speed across a large VDD vary, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) theme is proposed to chop off the IDC-SET of devices with a fast T SET. The SBWT theme reduces ninety nine+percent of the IDC-SET with an space penalty below 0.five%. A fabricated 512 row twenty eight nm one Mb ReRAM macro achieved TAC = 404 ns when VDD=0.27 V and confirmed the IDC-SET cutoff by the SBWT.