PROJECT TITLE :

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest - 2016

ABSTRACT:

This paper analyzes the advantages of using half-unit-biased (HUB) formats to implement floating-point (FP) arithmetic below a spherical-to-nearest mode from a quantitative purpose of read. Using the HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, as well as sticky-bit computation. This is shown for FP adders, multipliers, and converters. Experimental analysis demonstrates that the HUB formats and the corresponding arithmetic units maintain the same accuracy as the traditional ones. On the other hand, the implementation of those units, primarily based on basic architectures, shows that the HUB formats simultaneously improve area, speed, and power consumption. In addition, based mostly on the data obtained from the synthesis, an HUB single-precision adder is ~fourteen% faster however consumes 38% less space and 26% less power than the traditional adder. Similarly, an HUB single-precision multiplier is seventeenp.c faster, uses twenty twop.c less space, and consumes slightly less power than the conventional multiplier. At the same speed, the adder and therefore the multiplier achieve area and power reductions of up to fifty% and 40percent, respectively.