A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS

PROJECT TITLE :

A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS

ABSTRACT:

This paper presents a fourteen bit 35 MS/s successive approximation register (SAR) ADC that achieves a virtually constant seventy four.five dB peak SNDR up to Nyquist and an SFDR of ninety/ninety nine dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sampling capacitor from the input and thereby eases the ADC drive necessities significantly. Since the buffer's nonlinearity is cancelled by the SAR operation, a combine of basic supply followers can be used, adding solely 12.5 mW (twenty threep.c of the total power) to the power budget. The ADC includes a bandgap reference and a self-calibrated current steering DAC to close the SAR loop, which eliminates the necessity for an occasional-impedance off-chip reference. The planning occupies zero.236 mm$^2$ in forty nm CMOS and consumes a complete power of fifty four.five mW from its one.2/2.5 V provides, leading to an SNDR-primarily based Schreier FOM of 159.five dB at Nyquist.

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