A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in m CMOS


In this temporary, a 14-bit five hundred MS/s current-steering digital-to-analog converter (DAC) is proposed, that applies the novel grouped random rotation thermometer code (GRTC) and therefore the differential-quad switching (DQS) and has sensible dynamic performance while not calibrations. The GRTC suppresses the harmonics caused by component mismatches, while the DQS reduces the input-code transition-dependent distortion to realize a high spurious-free dynamic range (SFDR). A unit current cell with an intrinsic precision of twelve bits rather than 14 bits is used to reduce the active area, and the easy diagonal structure with a typical-centroid layout is adopted to scale back the gradient error. The measured SFDR of the proposed DAC is additional than eighty dBc below thirty five MHz and better than sixty eight dBc over the complete Nyquist bandwidth. The ability consumption of the DAC core is solely mW at 500 MS/s. The proposed DAC has been implemented in the Semiconductor Producing International Corporation (SMIC) 0.18- m CMOS method and occupies a full of life area of solely 0.fifty five .

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