PROJECT TITLE :
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
This paper presents a 13 bit fifty MS/s totally differential ring amplifier based mostly SAR-assisted pipeline ADC, implemented in sixty five nm CMOS. We have a tendency to introduce a replacement totally differential ring amplifier, which solves the issues of single-ended ring amplifiers while maintaining the advantages of high gain, fast slew based mostly charging and an nearly rail-to-rail output swing. We have a tendency to implement a switched-capacitor (SC) inter-stage residue amplifier that uses this new absolutely differential ring amplifier to allow accurate amplification while not calibration. In addition, a brand new floated detect-and-skip (FDAS) capacitive DAC (CDAC) switching method reduces the switching energy and improves linearity of first-stage CDAC. With these techniques, the prototype ADC achieves measured SNDR, SNR, and SFDR of 70.nine dB (11.5b), seventy one.three dB and eighty four.half dozen dB, respectively, with a Nyquist frequency input. The prototype achieves 13 bit linearity while not calibration and consumes 1 mW. This measured performance is corresponding to Walden and Schreier FoMs of six.9 fJ/conversion$cdot$step and 174.nine dB, respectively.
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