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PROJECT TITLE :

High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes

ABSTRACT:

This paper presents a unique construction scheme for nonbinary single-error correcting (SEC) codes that yields highspeed parallel decoding. The proposed theme utilizes two strategies, particularly, Improved and Reordered; these ways will be conjointly combined. Both of those methods scale back the amount of one's within the parity-check matrix (H-matrix) by reducing the 1's in every row vector. This ends up in a reduction in the gate depth within the syndrome generator, therefore achieving a shorter delay time for parallel decoding. In the proposed Improved method, for a single b-bit byte (i.e., 2b-ary image) error correcting code, the submatrix of the H-matrix corresponding to each b-bit byte is multiplied with an everyday matrix. The thus-referred to as improved submatrix is generated employing a heuristic (greedy) algorithm. The proposed Reordered technique selects the right b-bit bytes for deletion when shortening is performed. Simulation results show that the proposed scheme accomplishes a faster parallel decoding time than existing schemes. Furthermore, the proposed theme is applicable to any class of linear SEC codes, whereas existing schemes are applicable only to specific codes. In depth simulation results are provided to substantiate the viability of the proposed codes for faster parallel decoding (albeit incurring for many cases in modest increases of area and power dissipation because of additional circuitry).


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