PROJECT TITLE :
Analog hardware design of a memristor bridge synapse-primarily based multilayer neural network and its learning scheme is proposed. The utilization of memristor bridge synapse within the proposed architecture solves one amongst the main issues, concerning nonvolatile weight storage in analog neural network implementations. To make amends for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a changed chip-in-the-loop learning theme appropriate for the proposed neural network design is also proposed. In the proposed technique, the initial learning is conducted in software, and also the behavior of the software-trained network is learned by the hardware network by learning every of the only-layered neurons of the network independently. The forward calculation of the only-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a number computer. In contrast to standard chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in every epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware design along with the successful implementation of proposed learning on a 3-bit parity network, and on a automotive detection network is also presented.
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