Ultrahigh Density Memristor Neural Crossbar for On-Chip Supervised Learning


Although there are a number of candidates for future computing systems, memristor-based neural crossbar (NC) is considered particularly promising, thanks to their low power consumption, high density, and fault tolerance. But, their implementation remains hindered by the restrictions of CMOS neuron and learning cells. In this paper, we have a tendency to gift a memristor-based mostly NC that implements on-chip supervised learning. Rather than employing a normal CMOS neuron, a straightforward CMOS inverter realizes the activation operate. More importantly, we have a tendency to propose a compact learning cell that consists of a crossbar latch of two antiparallel oriented binary memristors. This design permits for higher density integration and could be naturally extended to a multilayer neural network. Using the CMOS forty-nm style kit and a physics-based mostly compact model of high-performance ferroelectric tunnel memristor, we have a tendency to performed transient simulations to validate the function of the proposed neural crossbar. Then, we have a tendency to construct a multilayer NC by cascading monolayer networks; thereby, enabling the network to be told nonlinearly separable functions (e.g., XOR perform). Finally, the fault tolerance is evaluated with Monte Carlo simulation. Analysis of simulation results demonstrates promising applications of our proposed neural crossbar for on-chip supervised learning.

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