Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography


As the feature size of semiconductor process further scales to sub-sixteen nm technology node, triple patterning lithography (TPL) has been regarded as one in all the most promising lithography candidates along with extreme ultraviolet, electron beam lithography, and directly self-assembly. M1 and call layers, which are sometimes deployed within commonplace cells, are the foremost critical and complicated parts for fashionable digital styles. Traditional design flow that ignores TPL in early stages could limit the potential to resolve all the TPL conflicts. In this paper, we tend to propose a coherent framework, including commonplace cell compliance and detailed placement, to enable TPL friendly style. Considering TPL constraints throughout early design stages, such as standard cell compliance, improves the layout decomposability. With the precoloring solutions of commonplace cells, we tend to present a TPL aware detailed placement where the layout decomposition and placement will be resolved simultaneously. Yet, we have a tendency to propose a linear dynamic programming to unravel TPL aware detailed placement with most displacement, that will achieve good trade-off in terms of runtime and performance. Experimental results show that our framework will achieve zero conflict, meanwhile can effectively optimize the stitch range and placement wire-length.

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