PROJECT TITLE :
A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies - 2017
Automatic synthesis of digital circuits has played a key role in obtaining high-performance styles. Whereas considerable work has been done in the past, rising device technologies decision for a want to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed. This paper presents a methodology for synthesis applicable to devices that support ternary logic. We present an algorithm for synthesis that mixes a geometrical representation with unary operators of multivalued logic. The geometric illustration facilitates scanning appropriately to obtain easy sum-of-products expressions in terms of unary operators. An implementation based on Python is described. The power of the approach lies in its applicability to a large choice of circuits. The proposed approach ends up in the savings of 26percent and twenty two% in transistor-count, respectively, for a ternary full-adder and a ternary content-addressable memory (TCAM) over the simplest existing styles. Furthermore, the proposed approach requires, on an average, but tenpercent of the quantity of the transistors compared with a recent decoder-based mostly design for numerous ternary benchmark circuits. Extensive HSPICE simulation results show roughly ninety twop.c reduction in power-delay product (PDP) for a 12 ×twelve TCAM and sixtypercent reduction in PDP for a 24-ternary digit barrel shifter over recent styles.
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