PROJECT TITLE :
Resistive Associative Processor
Associative Processor (AP) combines information storage and information processing, and functions simultaneously as a massively parallel array SIMD processor and memory. Traditionally, AP is predicated on CMOS technology, almost like other categories of massively parallel SIMD processors. The main component of AP may be a Content Addressable Memory (CAM) array. As CMOS feature scaling slows down, CAM experiences scalability issues. In this work, we propose and investigate an AP primarily based on resistive CAM-the Resistive AP (ReAP). We tend to show that resistive memory technology potentially permits scaling the AP from a few millions to a couple hundred several processing units on one silicon die. We tend to compare the performance and power consumption of a ReAP to a CMOS AP and a typical SIMD accelerator (GPU) and show that ReAP, although exhibiting higher power density, allows better scalability and better performance.
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