Layout geometry impact on nLDMOS devices for high-voltage ESD protection


N-channel, lateral, double-subtle MOS (NLDMOS) devices with finger-kind, sq.-type, and octagon-type layout styles are investigated and fabricated during a zero.5-μm 18 V CMOS-DMOS (CDMOS) process. The square-type nLDMOS achieves the highest ESD failure current of A and is also the device occupying the littlest chip area among the 3 layout designs. In read of the world potency, the square-type structure provides a lot of than thirty and 25p.c higher current handling capability per space than the traditional finger-kind and octagonal-type structures, respectively. As a result of of its higher space potency, the square-sort structure is a promising layout for nLDMOS in high-voltage ESD protection applications.

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