PROJECT TITLE :
Light Interference Map: A Prescriptive Optimization of Lithography-Friendly Layout
Achieving lithography-friendly layout typically involves repeated heuristic optimization and lithography simulations, and so is terribly time-consuming. We tend to propose a light interference map (LIM), in which the value of a explicit location represents the extent of potential lightweight interference to nearby patterns if some patterns are relocated (or some new patterns are introduced) to that location. LIM of a single pattern (e.g., contact or via) is obtained through repeated lithography simulations but only once. Superposition of single-pattern LIMs then yields the LIM of an arbitrary layout. LIM opens a possibility of prescriptive layout optimization, that is demonstrated through 2 example applications: optimizing some contact and via positions and SRAF placement. They're evaluated in 28 nm technology in terms of reduced defect chance.
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