Towards Low Power Approximate DCT Architecture for HEVC Standard - 2017


Video processing performed directly on IoT nodes is one of the foremost performance along with energy demanding applications for current IoT technology. So as to support real-time high-definition video, energy-reduction optimizations have to be introduced at all levels of the video processing chain. This paper deals with an economical implementation of Discrete Cosine Transform (DCT) blocks employed in video compression based mostly on the High Potency Video Coding (HEVC) standard. The proposed multiplierless 4-input DCT implementations contain approximate adders and subtractors that were obtained using genetic programming. So as to manage the complexity of evolutionary approximation and offer formal guarantees in terms of errors of key circuit parts, the worst and average errors were determined specifically by means of Binary decision diagrams. Below conditions of our experiments, approximate four-input DCTs show better quality/power trade-offs than relevant implementations obtainable within the literature. For example, 25% power reduction for the identical error was obtained compared with a recent highly optimized implementation.

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