PROJECT TITLE :
LLR-based Successive-Cancellation List Decoder for Polar Codes with Multi-bit Decision - 2017
Due to their capacity-achieving property, polar codes have become one in all the most engaging channel codes. To date, the successive cancellation list (SCL) decoding algorithm is the first approach that can guarantee outstanding error-correcting performance of polar codes. However, the hardware styles of the initial SCL decoder have large silicon area and long decoding latency. Although some recent efforts can cut back either the world or latency of SCL decoders, these two metrics still can't be optimized at the identical time. This paper, for the primary time, proposes a general log-probability-ratio (LLR)-primarily based SCL decoding algorithm with multi-bit call. This new algorithm, referred as LLR-2Kb-SCL, will verify 2K bits simultaneously for arbitrary K with the employment of LLR messages. Yet, a reduced-data-width scheme is presented to reduce the critical path of the sorting block. Then, based mostly on the proposed algorithm, a VLSI design of the new SCL decoder is developed. Synthesis results show that for an example (1024, 512) polar code with list size four, the proposed LLR-2Kb-SCL decoders achieve significant reduction in each area and latency as compared to previous works. As a result, the hardware potency of the proposed designs with K=two and three are two.33 times and 3.32 times of that of the state-of-the-art works, respectively.
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