Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity Sharing - 2017

PROJECT TITLE :

Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity Sharing - 2017

ABSTRACT:

As CMOS technology scales down, multiple cell upsets (MCUs) caused by a single radiation particle have become one amongst the foremost challenging reliability problems for reminiscences in house applications. In general, bits plagued by MCUs are typically physically shut. Error correction codes (ECCs) are commonly used to protect memory against MCUs. Recently, Matrix-primarily based codes are an interesting choice due to their low complexity decoding. The amount of parity bits matrix-primarily based codes required, which is related to the redundancy cells in recollections, isn't small. In this paper, an occasional redundancy theme for matrix-based codes is presented. Based on a brand new matrix arrangement, the proposed scheme combines the extended Hamming codes per row and parity codes per column with parity sharing. Compared to the present matrix-primarily based codes, the proposed theme maintains the identical correction capability, but prices a smaller range of parity bits by twenty fourp.c at most, a smaller space overhead by sixteen.24percent, and a lower power overhead by 26.04%, which make the new theme engaging for circuit implementations. Meanwhile, the MCUs chance of memories protected by the proposed theme can be reduced owning to less redundancy memory cells. However, the delay needed for the encoder and decoder of the proposed codes are in an exceedingly middle level among the present matrix-based mostly codes, that leads to that the proposed codes suit better for recollections with a strict requirement of area and power.

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