Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications - 2017


Voltage scaling has been used as a prominent technique to enhance energy potency in digital systems, cutting down provide voltage effects in quadratic reduction in energy consumption of the system. Reducing provide voltage induces timing errors in the system that are corrected through further error detection and correction circuits. In this paper we are proposing voltage over-scaling primarily based approximate operators for applications which will tolerate errors. We tend to characterize the basic arithmetic operators using different operating triads (combination of supply voltage, body-biasing theme and clock frequency) to get models for approximate operators. Error-resilient applications will be mapped with the generated approximate operator models to realize optimum trade-off between energy efficiency and error margin. Primarily based on the dynamic speculation technique, best attainable operating triad is chosen at runtime based on the user definable error tolerance margin of the applying. In our experiments in 28nm FDSOI, we have a tendency to achieve maximum energy efficiency of eighty nine% for basic operators like eight-bit and sixteen-bit adders at the value of 20percent Bit Error Rate (ratio of faulty bits over total bits) by operating them in near-threshold regime.

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