A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC - 2017


In this brief, a new very-giant-scale integrated (VLSI) integer remodel architecture is proposed for the High Potency Video Coding (HEVC) encoder. The design is intended primarily based on the signed bit-plane transform (SBT) matrices, that are derived from the bit-plane decompositions of the integer transform matrices in HEVC. Mathematically, an integer transform matrix will be equally expressed by the binary weighted sum of many SBT matrices that are solely composed of binary zero or ±one. The SBT matrices are very simple and have lower bit width than the first integer remodel in the form. The SBT matrices also are sparse and there are a number of zero components. The sparse characteristic of SBT matrices is terribly helpful for saving the addition operators of SBT. Within the proposed design, instead of the initial integer transform in high bit width, the video data will be respectively reworked with the SBT matrices in lower bit width. So, the delay of the transform unit circuit will be considerably reduced with the proposed SBT. Moreover, exploiting the redundant component characteristic of SBT matrices, in that the elements are 0 or ±one, the adder reuse strategy is proposed for our transform design, which can save the circuit space efficiently. The simulation results show that by employing the proposed strategies the VLSI rework design can be synthesized in a very correct area with a high operating frequency and low latency. The design can support all HEVC encoders coding ultra high-definition video sequences in real time.

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