Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression - 2017


Approximate arithmetic has recently emerged as a promising paradigm for several imprecision-tolerant applications. It will supply substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy needs. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the ensuing product terms to scale back the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of important methods is drastically reduced. A variety of multipliers with totally different bit-widths (four-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Style Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of sixty fivepercent in essential delay and virtually forty fivepercent in silicon space will be achieved for a 128-bit multiplier compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.00071 mean relative error. Additionally, we demonstrate the energy-accuracy trade-offs for various degrees of compression, achieved through configurable logic clustering. In evaluating the effectiveness of our approach, a case study image processing application showed up to 68.3% energy reduction with negligible losses in image quality expressed as peak signal-to-noise ratio (PSNR).

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