PROJECT TITLE :
Low Power 8-bit ALU Design Using Full Adder and Multiplexer - 2017
Arithmetic logic unit (ALU) is an important half of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we tend to describes eight-bit ALU using low power eleven-transistor full adder (FA) and Gate diffusion input (GDI) primarily based multiplexer. By using FA and multiplexer, we tend to have reduced power and delay of eight-bit ALU as compare to existing style. All style were simulated using Tanner EDA tool v15.zero in 32nm BSIM4 technology. Performance analyses were done with respect to power, delay and power delay product.
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