PROJECT TITLE :
Design And Analysis Of Combinational Coding Circuits Using Adiabatic Logic - 2017
Energy recovery logic or adiabatic logic is emerging as a replacement logic design vogue for implementation in fashionable technology with minimal impact on circuit heat generation. Adiabatic logic could be a design methodology for reversible logic in CMOS where the present flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advancements in reversible logic using and quantum computer algorithms enable for improved computer architectures. Production of cost effective secure Integrated Chips, like Smart Cards, needs hardware designers to consider tradeoffs in size, security, and power consumption. This paper presents a CMOS-primarily based new design approach for a low power adiabatic 4:two Priority Encoder and a 2:4 Decoder. The proposed designs are compared with the quality adiabatic logic styles– PFAL, ECRL and 2n2n2p, revealing lesser power consumption. The simulation is allotted in Tanner EDA software for frequency vary 200MHz – 800MHz.
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