Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders - 2017


This brief introduces a mixed-logic style method for line decoders, combining transmission gate logic, pass transistor twin-price logic, and static complementary metal-oxide semiconductor (CMOS). 2 novel topologies are presented for the two-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a fifteen-transistor topology aiming on high power-delay performance. Each normal and inverting decoders are implemented in each case, yielding a complete of four new designs. Furthermore, four new 4-16 decoders are designed by using mixed-logic a pair of-four predecoders combined with commonplace CMOS postdecoder. All proposed decoders have full-swinging capability and reduced transistor count compared to their standard CMOS counterparts. Finally, a selection of comparative spice simulations at 32 nm shows that the proposed circuits gift a important improvement in power and delay, outperforming CMOS in nearly all cases.

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