PROJECT TITLE :
Design and Low Power Magnitude Comparator - 2017
A low power 2 bit magnitude comparator has been proposed in the current work. The proposed magnitude comparator using the technology of coupling has been compared with the basic comparator circuit. The performance analysis of both the various comparators has been in serious trouble power consumption, delay and power delay-product (PDP) with VDD sweep. The simulations are carried on Mentor graphics (ELDO Spice) using 90nm CMOS technology at 1 V offer. The simulation results of the coupled magnitude comparator circuits is in sensible agreement in terms of power consumption at proportion of 60.twenty sixpercent in larger than function and fifty six.fourteenpercent in lesser than f unction and fifty nine.forty eightpercent in equals to function comparators.
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