A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier - 2017


A 1.8V CMOS chopper four-quadrant analog multiplier, assuming to function an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means that of chopper stabilization, while the multiplier's operation is predicated on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC zero.18 µm CMOS process.

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