On the Implementation of Computation-in-Memory Parallel Adder - 2017


Today's computer architectures suffer from many challenges, such as the close to finish of CMOS downscaling, the memory/Communication bottleneck, the ability wall, and the programming complexity. As a consequence, these architectures become inefficient in solving Big Data problems or general information intensive applications. Computation-in-memory (CIM) may be a novel architecture that tries to solve/alleviate the impact of those challenges using the identical device (i.e., the memristor) to implement the processor and memory in the identical physical crossbar. In order to analyze its feasibility comprehensive, this paper proposes 2 memristor implementations of a information intensive arithmetic application (i.e., parallel addition). To the most effective of our information, this is the first paper that considers the price of the complete architecture including both crossbar and its CMOS controller. The results show that CIM design generally and the CIM parallel adder in particular have a high scalability. CIM parallel adder achieves a minimum of 2 orders of magnitude improvement in energy and space as compared with a multicore-based parallel adder. Moreover, due to a wide range of memristor design strategies (such as Boolean logic), tradeoffs can be created between the world, delay, and energy consumption.

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