PROJECT TITLE :
Multi-operand logarithmic addition/subtraction based on Fractional Normalization - 2017
This paper presents a methodology for adding many numbers represented in the Logarithmic Range System (LNS). The proposed technique relies on the normalization towards the biggest input number. The distinct steps of the first two-input addition/subtraction using Fractional Normalization technique (FN)  are modified so as to achieve performance and scale back hardware needs. Three multi-operand adders are analyzed and compared: The first architecture uses the original FN method, the second uses an introduced 2-step changed FN (MFN) method, and therefore the third design uses full MFN methodology. The proposed multi-operand adders are synthesized and evaluated for complexity and performance using a sixty five-nm zero.9V UMC CMOS library, for the cases of four, 8, 16 inputs and an 11-bit word length.
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