Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor - 2017 PROJECT TITLE :Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor - 2017ABSTRACT:The widely using CMOS technology implementing with irreversible logic can hit a scaling limit beyond 20twenty and the foremost limiting factor is increased power dissipation. The irreversible logic is replaced by reversible logic to decrease the ability dissipation. The devices implemented with reversible logic gates will have demand for the upcoming future computing technologies as they consumes less power. Reversible logic has applications in Low Power VLSI, Quantum Computing, Nanotechnology and Optical computing. This paper proposes the design of a optimal fault tolerant Full adder / Full subtractor. For this logic circuit input parity and output parity is same hence it is known as parity preserving circuit. The proposed methodology need less complexity, less hardware, minimum range of gates, minimum range of garbage inputs and minimum variety of constant inputs than existing strategies. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects Probabilistic Error Analysis of Approximate Recursive Multipliers - 2017 On the Implementation of Computation-in-Memory Parallel Adder - 2017
