A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2017 PROJECT TITLE :A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2017ABSTRACT:Mounted-width multipliers are intensively used in many DSP applications whose accuracy and energy potency have an effect on the full digital system to a giant extent. To improve the computation accuracy, a Booth-encoded sign-digit-based conditional chance estimation approach is proposed. A symmetric error distribution is obtained by taking the sign little bit of the Booth-encoded multiplier into consideration when applying the conditional likelihood. Still, a more generalized mux-primarily based estimation technique is formulated for the circuit implementation, that reduces the delay time and power dissipation. Simulation results show that the proposed multiplier exhibits the simplest computation accuracy with the smallest amount energy per operation. It performs even better for those operand lengths that are not multiples of four. The maximum reduction on energy-delay-error product can reach 14.8% compared with all its contenders among numerous operand lengths. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers - 2017 High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017
