A Low Power Trainable Neuromorphic IntegratedCircuit That Is Tolerant to Device Mismatch - 2016

PROJECT TITLE :

A Low Power Trainable Neuromorphic IntegratedCircuit That Is Tolerant to Device Mismatch - 2016

ABSTRACT:

Random device mismatch that arises as a result of scaling of the CMOS (complementary metal-oxide semiconductor) technology into the deep submicrometer regime degrades the accuracy of analog circuits. Ways to combat this increase the complexity of design. We have developed a completely unique neuromorphic system called a trainable analog block (TAB), which exploits device mismatch as a means for random projections of the input to a higher dimensional area. The TAB framework is galvanized by the principles of neural population coding operating in the biological nervous system. Three neuronal layers, specifically input, hidden, and output, represent the TAB framework, with the amount of hidden layer neurons far exceeding the input layer neurons. Here, we tend to present measurement results of the primary prototype TAB chip designed employing a 65 nm method technology and show its learning capability for varied regression tasks. Our TAB chip is tolerant to inherent randomness and variability arising due to the fabrication method. Additionally, we tend to characterize each neuron and discuss the statistical variability of its tuning curve that arises thanks to random device mismatch, a fascinating property for the training capability of the TAB. We tend to additionally discuss the impact of the quantity of hidden neurons and therefore the resolution of output weights on the accuracy of the training capability of the TAB. We tend to show that the TAB may be a low Power System-the facility dissipation in the TAB with 456 neuron blocks is one.thirty eight µW.

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