Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs - 2016


Increased practical density with shrinking technology may lead to escalating power supply noise (PSN)-induced failures in the sphere. Furthermore, the low correlation between system-level purposeful take a look at and production check is creating it tough to raised screen parts that will fail in the sector due to PSN. To address these issues, during this paper, we tend to present a fully digital on-chip distributed sensor network to continuously monitor the PSN profile across the chip and generate a trace for diagnosis of any noise-induced failure at silicon validation, structural check, system check, and purposeful operation phases of system on chips (SoCs). The sensors capture PSN at a fine granularity and store the SoC's important standing bits. The sensor offers straightforward access and control with the help of scan chains. The sensor network has been designed within the twenty eight-nm standard cell library, and its performance is demonstrated in the physical style of OpenSPARCT1 multicore processor SoC.

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