A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation - 2016 PROJECT TITLE : A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation - 2016 ABSTRACT: The ability budget is expected to limit the portion of the chip that we tend to will power ON at the upcoming technology nodes. This problem, referred to as the use wall or dark silicon, is changing into increasingly serious. With the introduction of 3-D integrated circuits (ICs), it is probably to become a lot of severe. Therefore, how to take advantage of the extra transistors, made on the market by Moore's law and the onset of 3-D ICs, at intervals the ability budget poses a significant challenge to system designers. To address this challenge, we have a tendency to propose a three-D hybrid design consisting of a CPU layer with multiple cores, a field-programmable gate array (FPGA) layer, and a DRAM layer. The architecture is meant for low power without sacrificing performance. The FPGA layer is capable of supporting a massive range of accelerators. It's placed adjacent to the CPU layer, with a Communication mechanism that permits it to access CPU information caches directly. This permits quick switches between these 2 layers. This architecture reduces the ability and energy significantly, at higher or similar performance. This then alleviates the dark silicon problem by letting us power ON more elements to realize higher performance. We evaluate the proposed architecture through a replacement framework we tend to have developed. Relative to the out-of-order CPU, the accelerators on the FPGA layer can scale back operate-level power by 6.nine× and energy-delay product (EDP) by 7.two×, and application-level power by one.nine× and EDP by 2.2×, whereas delivering similar performance. For the whole system, this interprets to a 47.5p.c power reduction relative to a baseline system that consists of a CPU layer and a DRAM layer. This conjointly translates to a 72.ninepercent power reduction relative to an alternative system that consists of a CPU layer, an L3 cache layer, and a DRAM layer. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Field Programmable Gate Arrays Low-Power Electronics Parallel Architectures Performance Evaluation Power Aware Computing Multiprocessing Systems Cache Storage Dram Chips Three-Dimensional Integrated Circuits Low-Power FPGA Design Using Memorization-Based Approximate Computing - 2016 Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs - 2016
