Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia - 2016


This paper presents the look of a absolutely integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations within the ECG signal with high sensitivity and precision. 2 databases of the center signal recordings from the MIT PhysioNet and also the American Heart Association were used as a validation set to guage the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the general classification accuracy was found to be eighty six% on the out-of-sample validation data with three-s window size. The design of the proposed ESP was implemented using 65-nm CMOS process. It occupied zero.112-mm2 space and consumed a pair of.seventy eight-µW power at an operating frequency of ten kHz and from an operating voltage of one V. It's value mentioning that the proposed ESP is the primary ASIC implementation of an ECG-based processor that's used for the prediction of ventricular arrhythmia up to three h before the onset.

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