PROJECT TITLE :
Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication - 2016
Double-edged pulsewidth modulation (DPWM) is a smaller amount sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits info at a totally different rate than a synchronous supply. This paper presents an eight-/nine-bit line-coding theme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the dimensions of buffering needed in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for top-speed data recovery. The DPWM transceiver is implemented during a forty five-nm CMOS Silicon on insulator and operates at 10 Gbit/s with ten-twelve bit error rate and consumes ninety six mW. The power consumption of the eight-/9-bit coding hardware is one.five mW at 10 Gbit/s demonstrating low-power overhead.
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