PROJECT TITLE :
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols - 2016
In a fashionable system-on-chip design, tons of cores and intellectual properties can be integrated into a single chip. To be appropriate for top-performance interconnects, designers increasingly adopt advanced interconnect protocols that support novel mechanisms of parallel accessing, together with outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to make your mind up in-order or out-of-order properties. However, these advanced protocols might lead to transaction deadlocks that do not occur in ancient protocols. To prevent the deadlock downside, current solutions stall suspicious transactions and in certain cases, many such stalls will incur serious performance penalty. During this temporary, we tend to propose a completely unique ID assignment mechanism that guarantees the issued transactions to be deadlock-free and leads to vital reduction in the amount of transaction stalls issued by masters. Our experimental results show encouraging performance improvements compared with previous works with little hardware and power overheads.
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